Digital Design · Circuit Simulation · VLSI Engineering
A collection of my hardware simulation and digital design projects showcasing expertise in Verilog, eSim, MATLAB, and TL-Verilog
Leveraging Large Language Models (LLMs) and TL-Verilog to modernize existing Verilog codebases by reducing code size, improving maintainability, enhancing configurability, and identifying potential bugs. This project demonstrates the intersection of AI and hardware design.
Key Features:
A sophisticated hardware-based ticketing system implemented in Verilog, providing secure and hack-resistant cinema ticket booking directly at the hardware level. This project demonstrates advanced FSM design and security principles in digital systems.
Key Features:
Complete implementation of Universal Asynchronous Receiver-Transmitter (UART) protocol in Verilog, featuring comprehensive parity checking, baud rate configuration, and full-duplex communication capabilities with extensive simulation and verification.
Key Features:
An intelligent voting system utilizing advanced image processing and OpenCV in MATLAB to reduce election costs, minimize manual identification errors, and enable secure remote voting capabilities. Features real-time facial recognition for voter verification.
Key Features:
Design, simulation, and verification of Sawtooth and Triangular Wave Generators using eSim, an open-source EDA tool. Implements operational amplifier-based circuits utilizing comparators and integrators for precise waveform generation in analog signal processing.
Key Features:
Circuit Components:
Verilog, System-Verilog, TL-Verilog, FSM Design, RTL Coding
eSim, SPICE, Analog/Digital Circuit Design, Op-Amp Applications
Makerchip, Open-Source EDA, Simulation & Verification
MATLAB, Python for Verification, Testbench Development
Proposal to leverage Large Language Models (LLMs) and TL-Verilog to modernize existing Verilog codebases. Focuses on reducing code size, improving maintainability, enhancing configurability, and identifying potential bugs through AI-assisted code transformation.
Mentor: Steve Hoover
Organisation: Free and Open Source Silicon (FOSSi) Foundation
Focus Area: AI-Assisted Hardware Design, Code Quality
Research project on the design and simulation of Sawtooth and Triangular Wave Generators for advanced circuit applications. Implemented using eSim, an open-source EDA tool, with focus on operational amplifier-based circuit design.
Organisation: FOSSEE (Free/Libre and Open Source Software for Education), IIT Bombay
Focus Area: Analog Circuit Design, Open-Source EDA Tools
Tools Used: eSim, Python for verification
Platform: EdX
Mentor: Steve Hoover
Gained TL-Verilog, Makerchip, advanced Verilog, and RISC-V architecture knowledge through hands-on CPU design.
View CertificatePlatform: NPTEL
Mastered Assembly language programming, hardware interfacing, and microprocessor core components for embedded systems design.
View CertificatePlatform: EdX
Gained advanced MATLAB and signal processing skills for real-world hardware simulation and analysis projects.
View CertificatePlatform: NPTEL
Learned CMOS technology, the cutting edge of future semiconductor and chip technology, including layout and design principles.
View CertificatePlatform: VLSI System Design
Learned Skywater PDK and its usage in circuit building, including open-source VLSI design methodologies.
View CertificateExplore my AI, Machine Learning, and Software Engineering projects
View Software Projects