Hardware & VLSI Projects

Digital Design · Circuit Simulation · VLSI Engineering

A collection of my hardware simulation and digital design projects showcasing expertise in Verilog, eSim, MATLAB, and TL-Verilog

Digital Design & Simulation Projects

Verilog to TL-Verilog Conversion

Verilog to TL-Verilog Conversion

Leveraging Large Language Models (LLMs) and TL-Verilog to modernize existing Verilog codebases by reducing code size, improving maintainability, enhancing configurability, and identifying potential bugs. This project demonstrates the intersection of AI and hardware design.

TL-Verilog Verilog LLMs Makerchip

Key Features:

  • Automated code optimization using AI
  • Bug detection and code quality improvement
  • Enhanced code maintainability and readability
  • Configurable hardware design patterns
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Smart Cinema Ticket Booking System

Smart Cinema Ticket Booking System

A sophisticated hardware-based ticketing system implemented in Verilog, providing secure and hack-resistant cinema ticket booking directly at the hardware level. This project demonstrates advanced FSM design and security principles in digital systems.

Verilog FSM Design Digital Logic Security

Key Features:

  • Hardware-level security implementation
  • Finite State Machine (FSM) based booking logic
  • Real-time seat availability management
  • Robust error handling and validation
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UART Protocol Implementation

UART Protocol Implementation

Complete implementation of Universal Asynchronous Receiver-Transmitter (UART) protocol in Verilog, featuring comprehensive parity checking, baud rate configuration, and full-duplex communication capabilities with extensive simulation and verification.

Verilog UART Serial Communication Testbench

Key Features:

  • Configurable baud rate and data width
  • Parity checking (even, odd, none)
  • Full-duplex asynchronous communication
  • Comprehensive testbench validation
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Automated Voting System

Automated Voting System

An intelligent voting system utilizing advanced image processing and OpenCV in MATLAB to reduce election costs, minimize manual identification errors, and enable secure remote voting capabilities. Features real-time facial recognition for voter verification.

MATLAB OpenCV Image Processing Face Recognition

Key Features:

  • Automated voter identification using facial recognition
  • Advanced image processing algorithms
  • Fraud detection and prevention mechanisms
  • Remote voting capability with security
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Wave Generators using eSim

Waveform Generators using eSim

Design, simulation, and verification of Sawtooth and Triangular Wave Generators using eSim, an open-source EDA tool. Implements operational amplifier-based circuits utilizing comparators and integrators for precise waveform generation in analog signal processing.

eSim Analog Design Op-Amp Circuits Circuit Simulation

Key Features:

  • Triangular wave with equal rise/fall times
  • Sawtooth wave with asymmetric slope control
  • Variable DC input for waveform transition
  • Applications in PWM, synthesizers, and oscilloscopes

Circuit Components:

  • Op-amp based comparator and integrator design
  • Potentiometer for adjustable waveform shaping
  • Verified through Python plots and multimeter readings
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Technical Expertise

Digital Design

Verilog, System-Verilog, TL-Verilog, FSM Design, RTL Coding

Circuit Simulation

eSim, SPICE, Analog/Digital Circuit Design, Op-Amp Applications

EDA Tools

Makerchip, Open-Source EDA, Simulation & Verification

HDL & Scripting

MATLAB, Python for Verification, Testbench Development

Open Source VLSI Contributions

FOSSi Foundation

Verilog to TL-Verilog Conversion Initiative

Proposal to leverage Large Language Models (LLMs) and TL-Verilog to modernize existing Verilog codebases. Focuses on reducing code size, improving maintainability, enhancing configurability, and identifying potential bugs through AI-assisted code transformation.

Mentor: Steve Hoover

Organisation: Free and Open Source Silicon (FOSSi) Foundation

Focus Area: AI-Assisted Hardware Design, Code Quality

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FOSSEE IIT Bombay

Advanced Waveform Generator Research

Research project on the design and simulation of Sawtooth and Triangular Wave Generators for advanced circuit applications. Implemented using eSim, an open-source EDA tool, with focus on operational amplifier-based circuit design.

Organisation: FOSSEE (Free/Libre and Open Source Software for Education), IIT Bombay

Focus Area: Analog Circuit Design, Open-Source EDA Tools

Tools Used: eSim, Python for verification

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Hardware & VLSI Certifications

Building a RISC-V CPU Core

Platform: EdX

Mentor: Steve Hoover

Gained TL-Verilog, Makerchip, advanced Verilog, and RISC-V architecture knowledge through hands-on CPU design.

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Microprocessors and Interfacing

Platform: NPTEL

Mastered Assembly language programming, hardware interfacing, and microprocessor core components for embedded systems design.

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MATLAB Essentials

Platform: EdX

Gained advanced MATLAB and signal processing skills for real-world hardware simulation and analysis projects.

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CMOS Digital VLSI Design

Platform: NPTEL

Learned CMOS technology, the cutting edge of future semiconductor and chip technology, including layout and design principles.

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VLSI System Design

Platform: VLSI System Design

Learned Skywater PDK and its usage in circuit building, including open-source VLSI design methodologies.

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Interested in Software Projects?

Explore my AI, Machine Learning, and Software Engineering projects

View Software Projects